1. Field of the Invention
This invention relates to the field of multiprocessor computer systems and, more particularly, to multiprocessor computer systems which operate in a cluster mode to provide fault isolation.
2. Description of the Relevant Art
Multiprocessing computer systems include two or more processors which may be employed to perform computing tasks. A particular computing task may be performed upon one processor while other processors perform unrelated computing tasks. Alternatively, components of a particular computing task may be distributed among multiple processors to decrease the time required to perform the computing task as a whole. Generally speaking, a processor is a device configured to perform an operation upon one or more operands to produce a result. The operation is performed in response to an instruction executed by the processor.
A popular architecture in commercial multiprocessing computer systems is the symmetric multiprocessor (SMP) architecture. Typically, an SMP computer system comprises multiple processors connected through a cache hierarchy to a shared bus. Additionally connected to the bus is a memory, which is shared among the processors in the system. Access to any particular memory location within the memory occurs in a similar amount of time as access to any other particular memory location. Since each location in the memory may be accessed in a uniform manner, this structure is often referred to as a uniform memory architecture (UMA).
Processors are often configured with internal caches, and one or more caches are typically included in the cache hierarchy between the processors and the shared bus in an SMP computer system. Multiple copies of data residing at a particular main memory address may be stored in these caches. In order to maintain the shared memory model, in which a particular address stores exactly one data value at any given time, shared bus computer systems employ cache coherency. Generally speaking, an operation is coherent if the effects of the operation upon data stored at a particular memory address are reflected in each copy of the data within the cache hierarchy. For example, when data stored at a particular memory address is updated, the update may be supplied to the caches which are storing copies of the previous data. Alternatively, the copies of the previous data may be invalidated in the caches such that a subsequent access to the particular memory address causes the updated copy to be transferred from main memory. For shared bus systems, a snoop bus protocol is typically employed. Each coherent transaction performed upon the shared bus is examined (or xe2x80x9csnoopedxe2x80x9d) against data in the caches. If a copy of the affected data is found, the state of the cache line containing the data may be updated in response to the coherent transaction.
Unfortunately, shared bus architectures suffer from several drawbacks which limit their usefulness in multiprocessing computer systems. A bus is capable of a peak bandwidth (e.g. a number of bytes/second which may be transferred across the bus). As additional processors are attached to the bus, the bandwidth required to supply the processors with data and instructions may exceed the peak bus bandwidth. Since some processors are forced to wait for available bus bandwidth, performance of the computer system suffers when the bandwidth requirements of the processors exceeds available bus bandwidth.
Additionally, adding more processors to a shared bus increases the capacitive loading on the bus and may even cause the physical length of the bus to be increased. The increased capacitive loading and extended bus length increases the delay in propagating a signal across the bus. Due to the increased propagation delay, transactions may take longer to perform. Therefore, the peak bandwidth of the bus may decrease as more processors are added.
These problems are further magnified by the continued increase in operating frequency and performance of processors. The increased performance enabled by the higher frequencies and more advanced processor microarchitectures results in higher bandwidth requirements than previous processor generations, even for the same number of processors. Therefore, buses which previously provided sufficient bandwidth for a multiprocessing computer system may be insufficient for a similar computer system employing the higher performance processors.
Another approach for implementing multiprocessing computer systems is a scalable shared memory (SSM) architecture (also referred to as a distributed shared memory architecture). An SSM architecture includes multiple nodes within which processors and memory reside. The multiple nodes communicate via a network coupled therebetween. When considered as a whole, the memory included within the multiple nodes forms the shared memory for the computer system. Typically, directories are used to identify which nodes have cached copies of data corresponding to a particular address. Coherency activities may be generated via examination of the directories.
SSM systems are scaleable, overcoming the limitations of the shared bus architecture. Since many of the processor accesses are completed within a node, nodes typically have much lower bandwidth requirements upon the network than a shared bus architecture must provide upon its shared bus. The nodes may operate at high clock frequency and bandwidth, accessing the network when needed. Additional nodes may be added to the network without affecting the local bandwidth of the nodes. Instead, only the network bandwidth is affected.
In a typical SSM system, a global domain is created by way of the SSM protocol which makes all the memory attached to the global domain look like one shared memory accessible to all of its processors. A global domain typically runs a single kernel. Hardware provides conventional MMU (memory management unit) protection, and the kernel manages mappings (e.g. reloading of key registers on context switches) to allow user programs to co-exist without trusting one another. Since the nodes of a global domain share memory and may cache data, a software error in one node may create a fatal software error which may crash the entire system. Similarly, a fatal hardware error in one node will typically cause the entire global domain to crash.
Accordingly, in another approach to multiprocessing computer systems, clustering may be employed to provide greater fault protection. Unlike SSM approaches, the memory of one node in a cluster system is not freely accessible by processors of other cluster nodes. Likewise, the I/O of one node is typically not freely accessible by processors of other nodes. While memory is not freely shared between nodes of a cluster, a cluster allows nodes to communicate with each other in a protected way using an interconnection network which is virtualized and protected via operating system abstractions. Normally, each node of a cluster runs a separate kernel. Nodes connected in a cluster should not be able to spread local faults, both hardware and software, that would crash other nodes.
While the concept of clustering for providing protection in multiprocessing computer systems is generally known, various limitations have been associated with cluster systems. These limitations include the lack of addressing schemes which cover a large number of nodes, the lack of flexible protection mechanisms that protect a node from software and hardware failures in other nodes, the lack of protocols which are extensible that allow communications to be set up as xe2x80x9chopsxe2x80x9d through other nodes to thereby allow efficient interconnect networks, and the lack of error reporting mechanisms that are applicable to protocols running at a user-level.
Cluster systems allow memory in remote cluster nodes to be mapped into a local node""s virtual address space; in order to implement this efficiently, it is desirable to map all of the available remote memory into the local node""s physical address space. While currently-existing technology can accomplish this operation, there are limitations in some of the methods used.
Some of these limitations are the inability to use the vast majority of an SMP""s hardware address space to access remote memory; the inability to do fine-grained sharing of an SMP""s address space among multiple hardware interfaces, to support load balancing between them; and the inability to transfer the handling of transactions destined for a particular remote node from one hardware interface to another, without changing the physical addresses being used by currently-running application programs.
It is thus desirable to provide a fast and reliable communication mechanism in a cluster system which allows for efficient implementation of user and kernel-level communication protocols. It is further desirable to allow flexible use of a system""s address base.
In one embodiment, a multiprocessing computer system includes a plurality of nodes. The plurality of nodes may be interconnected through a global interconnect network which supports cluster communications. An initiating node may launch a request to a remote node""s memory. In one specific implementation, the address base of the system is divided into xe2x80x9cslicesxe2x80x9d. Different slices may correspond to the local memory of differing cluster nodes. The system interface of each node advantageously includes a lookup table which is used to associate selected address regions, or slices, with specific remote nodes for which the slices are local. Accordingly, when a processor within a node initiates a transaction on a local bus, the system interface of that node accesses its lookup table to determine whether that transaction should be conveyed to a remote node, as determined by the corresponding entry of the lookup table for that transaction""s address. Otherwise, the transaction is a local transaction and is not conveyed upon the global bus network.
More than one system interface may be provided in a particular node. In one particular implementation, a specific slice may have a valid entry in more than one of the node""s system interfaces. In that case, the different system interfaces may be initialized to handle a subset of the accesses for that slice. For example, one system interface may handle even address transactions for that slice and the other system interface may handle the odd address transactions for that slice. In this manner, increased bandwidth to one specific node may be advantageously provided.
In another specific implementation wherein several system interfaces reside in one node, a specific cluster slice may have a valid lookup table entry in only one of the system interfaces. In this manner, increasing the number of system interfaces may advantageously accommodate increased connectivity for the node with respect to the number of other nodes to which the node may be connected.
A multiprocessing computer system which implements a system as described herein may advantageously allow the use of a large portion of a local node""s addressable space to be used to access remote memory. Furthermore, relatively fine-grained sharing of the local buses address space among multiple system interfaces may allow load balancing. Furthermore, the mechanism may advantageously allow the transfer of the handling of transactions destined to a particular remote node from one system interface to another system interface without changing the physical addresses being used by the currently-running application programs.